This book presents models and procedures to design pipeline analog-to-digital converters
compensating for device inaccuracies so that high-performance specs can be met within short
design cycles. These models are capable of capturing and predicting the behavior of pipeline
data converters within less than half-a-bit deviation versus transistor-level simulations. As
a result far fewer model iterations are required across the design cycle. Models described in
this book accurately predict transient behaviors which are key to the performance of
discrete-time systems and hence to the performance of pipeline data converters.
