Nowadays using SRAM based FPGAs in space missions is increasingly considered due to their
flexibility and reprogrammability. A challenge is the devices sensitivity to radiation effects
that increased with modern architectures due to smaller CMOS structures. This work proposes
fault tolerance methodologies that are based on a fine grain view to modern reconfigurable
architectures. The focus is on SEU mitigation challenges in SRAM based FPGAs which can result
in crucial situations.
