Low substrate lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied
by device research and integration professionals in CMOS logic and analog products from the
early 1970s. The author of this book previously composed an e-book in this area where he and
his co-authors performed original simulation and modeling work on MOSFET threshold voltage and
demonstrated that through efficient manipulation of threshold voltage values at lower substrate
temperatures superior degrees of reduction of subthreshold and off-state leakage current can
be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In
this book the author explores other device parameters such as channel inversion carrier
mobility and its characteristic evolution as temperature on the die varies from 100-300 K.
Channel mobility affects both on-state drain current and subthreshold drain current and both
drain current behaviors at lower temperatures have been modeled accurately and simulated for a
1 ??m channel length n-MOSFET. In addition subthreshold slope which is an indicator of how
speedily the device drain current can be switched between near off current and maximum drain
current is an important device attribute to model at lower operating substrate temperatures.
This book is the first to illustrate the fact that a single subthreshold slope value which is
generally reported in textbook plots and research articles is erroneous and at lower gate
voltage below inversion subthreshold slope value exhibits a variation tendency on applied gate
voltage below threshold i.e. varying depletion layer and vertical field induced surface band
bending variations at the MOSFET channel surface. The author also will critically review the
state-of-the art effectiveness of certain device architectures presently prevalent in the
semiconductor industry below 45 nm node from the perspectives of device physical analysis at
lower substrate temperature operating conditions. The book concludes with an emphasis on
modeling simulations inviting the device professionals to meet the performance bottlenecks
emanating from inceptives present at these lower temperatures of operation of today's 10 nm
device architectures.
